Semiconductior device and memory card using same

ABSTRACT

A semiconductor device capable of achieving downsizing without reducing the power supply efficiency and capable of reducing switching noises and a memory card using the same are disclosed. The device comprises a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit for controlling an output voltage at a nearby location of the final stage, and one or more internal elements to which the final output voltage is supplied. A primary voltage booster circuit at the first stage includes an inductance element, a switching element, a diode and a driver circuit. At a metal core part of the inductance element, a metal wiring line is used, which was formed by use of a fabrication process of semiconductor integrated circuits, while employing for its core part an inter-wiring layer dielectric film that was formed using the fabrication process. In addition, the switching element and the diode are arranged so that portions thereof are disposed beneath the inductance element.

BACKGROUND OF THE INVENTION

The present invention relates to semiconductor devices having internalcircuitry for producing either a voltage higher in potential than thepower supply voltage or a lower voltage than an input voltage, whichvoltage is used to operate internal circuit elements. This inventionalso relates to electronic equipment such as memory cards usingsemiconductor devices of the type stated above.

As handheld or “mobile” information tools come into wide use, chancesfor hand-carrying data in the form of plug-in type semiconductor storagemedia increase, resulting in a likewise increase in amount of thecarry-on data of high-quality images, audio and motion pictures as wellas text documents. To this end, demands grow for non-volatile memoriesthat are inevitable for conservation of these kinds of data—inparticular, electrically erasable programmable read only memory (EEPROM)chips. An EEPROM with “all-at-once” erasability is called flash EEPROM(referred to as “flash memory” hereinafter), which is widely used as alarge-capacity/low-cost nonvolatile memory as it performs an eraseoperation at a time on a per-block basis to thereby offer the capabilityto achieve higher integration densities.

While IC cards with a built-in flash memory are becoming popularized ascell phone-use cards, credit cards, cash cards and others, the quest forattaining multi-functionalities increases, which leads to a need forembedding a large-capacity memory capable of storing an operating system(OS) and application programs plus data while at the same time offeringreliable functionality with lower power consumption. Due to this, thereare advances in technologies for micro-fabrication of microcomputers andflash memories to be mounted in IC cards and also for lowering thesupply voltage.

In addition, as consumer equipment grows in performance andfunctionality, flash memory-embedded microcomputers also are required tooffer enhanced speed performances with lower power consumption,resulting in advances in downsizing and reduction of the power supplyvoltage of flash memory-embedded microcomputers or system-on-chip (SoC)devices.

In flash memories, a higher voltage than the supply voltage is necessaryduring data writing and erasing operations; for this reason, a voltageraising or “boosting” circuit is provided within a flash memory LSI. Acircuit scheme, called the charge pump circuit, is widely used as suchthe booster circuit. An example of the charge pump circuit is shown inFIG. 29, wherein multiple stages of basic unit circuits each having acapacitor 160 and a diode 170 are serially connected together. A pulsatebias voltage is applied to one end of such capacitor, causing electricalcharge to move toward the next step on a per-clock basis for potentialriseup of the voltage of a capacitive load. Another example of thecharge pump circuit is the so-called “voltage-doubling rectification”scheme, which charges up capacitors in parallel and then switches to aseries connection to thereby obtain a high voltage required.

Further alternative voltage booster circuit schemes are available, whichinclude a scheme for using a DC-DC converter circuit and a technique forusing in combination a DC-DC converter circuit and a charge pumpcircuit, as disclosed in Japanese Application Patent Laid-openPublication Nos. Hei 07-21791 and Hei 08-297986, respectively.

Additionally, in voltage-drop circuit-embedded LSIs to be used whenrequiring a lower voltage than an input voltage, a dropper type circuitis employed; alternatively, when using a chopper type voltage dropcircuit, inductors for use therein are discrete components, which areprovided external to an LSI chip.

While the quest grows for miniaturization and lower power supply voltageof microcomputers or flash memories to be built in IC cards or flashmemory-embedded microcomputers, voltages for use during write and eraseoperations of flash memories are hardly lowered due to the operationprinciples thereof even though microfabrication technologies are muchadvanced. For this reason, a difference between input and outputvoltages of the voltage booster circuitry tends to further increase infuture.

With the charge pump scheme used for prior known voltage boostercircuits, a potentially raised voltage per pump stage becomes a voltagewith its potential equal to a difference between the power supplyvoltage and a diode drop-down voltage. Thus, as the supply voltage of anLSI decreases with advances in device miniaturization, the boostedvoltage per pump stage becomes smaller. This results in the number ofstages required for boosting up to a desired voltage increasing with adecrease in supply voltage, which leads to a likewise increase in layoutarea of circuits. As the memory capacity increases to provide largestorage capacities of 1, 4 and 16 gigabits (Gb), such area increasebecomes more noticeable. While the processors and memories will belowered in voltage due to advances in microfabrication techniques, theflash memory's write and erase voltages are hardly changed. Thus,downsizing the power supply circuitry must be an important issue forLSIs of the type having built-in voltage booster circuits.

On the other hand, in known DC-DC converter schemes or DC-DCconverter/charge-pump combining schemes, inductance element fabricationrequires a “special” process not found in standard LSI processes—thatis, a thick-film process aimed at magnetic core formation andachievement of lower resistance. Unfortunately the thick-film wiring isfaced with a problem which follows: at circuit portions other than theinductance elements such as for example word lines of a memory, thewiring aspect becomes higher, resulting in the difficulty inmicrofabrication. This in turn makes it difficult to fabricate on-chipinductance elements. An approach to avoiding this risk is to the use ofa method having the steps of forming inductance elements at separateprocesses and then bonding them together or alternatively an externalconnection method. For the reasons stated above, the known DC-DCconverter schemes fail to be the voltage booster circuit scheme suitablefor standard LSI processes.

Also note that voltage drop circuit-embedded LSIs also suffer fromproblems which follow: large power dissipation due to the droppercircuit designs, or a large parts-mount area due to the use of choppercircuits externally associated with external inductors.

It is therefore an object of the present invention to provide asemiconductor device capable of achieving size reduction of itsassociated power supply unit while using currently establishedsemiconductor fabrication technologies and also capable of reducingswitching noises. Another object of the invention is to provide a memorycard using the semiconductor device.

SUMMARY OF THE INVENTION

In accordance with one aspect of this invention, there is provided asemiconductor device which causes an internal circuit to generate ahigher voltage than the power supply voltage for operating internalcircuit elements. The semiconductor device comprises a plurality ofstages of voltage booster circuits for potentially raising the powersupply voltage up to a predetermined final output voltage, an outputvoltage control means connected to a voltage booster circuit adjacent toa final stage of said voltage booster circuits, and an internal elementto which an output of the voltage booster circuits is supplied, whereina first stage voltage booster circuit of the voltage booster circuitsfor raising the power supply voltage up to a primary voltage isconstituted from a converter circuit including an inductance element, aswitching element and a diode, wherein voltage booster circuits in backof the first stage for raising the primary voltage up to thepredetermined final voltage are each configured from a charge pumpcircuit including a capacitance element and a diode or a convertercircuit including an inductance element, a switching element and adiode, wherein the inductance element and the switching element plus thediode making up the voltage booster circuit as well as the outputvoltage control means and the internal element are formed on asemiconductor substrate, and wherein the output voltage control meanscontrols the voltage booster circuit near the final stage in such a waythat the final output of the booster circuits becomes a potentiallystabilized predetermined output voltage and then supplies such theoutput to the above-noted internal element.

The invention also provides a semiconductor device which is arranged todrive the gate of a switching element by a higher voltage than an inputpower supply voltage.

The invention also provides a semiconductor device in which a gatedriver circuit for driving the gate of a switching element has a voltagebooster circuit, wherein a higher voltage than the input supply voltageis used to drive the gate of the switching element.

The invention also provides a semiconductor device which is arranged tocontrol the voltage booster circuit at the final stage in such a mannerthat the final output of the group of booster circuits becomes apotentially stabilized prespecified output voltage.

The invention also provides a semiconductor device which controls avoltage booster circuit immediately before the final-stage boostercircuit so that the final output of the booster circuit group becomes apotentially stabilized prespecified output voltage.

The invention provides a semiconductor device which ensures that atleast one of converter circuits is designed so that either a potentialboost ratio or a switching duty ratio is kept at a preset value during aboosting operation.

The invention also provides a semiconductor device which ensures that atleast one of converter circuits is such that either its boost ratio orswitching duty ratio is kept at a preset value during a boostingoperation, and which has a means for setting the boost ratio or theswitching duty ratio at a given value.

The invention also provides a semiconductor device having convertercircuits, at least one of which is more than or equal to 10 MHz inswitching frequency thereof.

The invention also provides a semiconductor device having an inductanceelement which is a parallel-connection type inductance element made upof multilayered metal wiring lines and a dielectric film providedbetween such wiring layers, wherein the multilayer metal wires areconnected in parallel.

In accordance with another aspect of the invention, a semiconductordevice having an internal circuit which generates a higher voltage thanthe power supply voltage for operating an internal element(s) and amemory card using the same are provided. The device comprises aplurality of stages of potential booster circuits for boosting the powersupply voltage up to a predetermined final output voltage, a voltagecontrol unit for control of an output voltage near the final stage, andan internal circuit element to which the final output voltage issupplied, wherein the plural stages of booster circuits include aconverter circuit which at least has an inductance element, a switchingelement, a diode and a driver circuit for driving the switching element,and wherein the inductance element within the converter circuit at leastincludes a metal wiring line that is formed in the same process of metalwires for use as power supply wires.

The invention is also directed to a semiconductor device having aninternal circuit that generates a higher voltage than the power supplyvoltage for operating an internal element(s) and a memory card using thesame. The device comprises a plurality of stages of potential boostercircuits for boosting the power supply voltage up to a predeterminedfinal output voltage, a voltage control unit for control of an outputvoltage at or near the final stage, and an internal circuit element towhich the final output voltage is supplied, wherein a primary boostercircuit at the first stage comprises a converter circuit which at leasthas an inductance element, a switching element, a diode and a drivercircuit for driving the switching element, and wherein the switchingelement and the diode are partially disposed to underlie the inductanceelement.

Alternatively, the switching element and the diode which are partlydisposed beneath the inductance element are such that a drain-sideregion of the switching element and an anode-side region of the diodeare laid out to oppose each other on a semiconductor substrate, whereinmore than two sets of combination units, each having a combination ofswitching element and diode with the both regions being electricallyconnected together, are connected in parallel.

Alternatively the device may comprise a potential step-down circuit forreducing an input voltage to a prespecified final output voltage, whichcircuit consists essentially of an inductance element, a switchingelement, a diode, a driver circuit and a control circuit, wherein theswitching element and the diode are partially disposed to underlie theinductance element.

An alternative configuration is that the switching element and the diodewhich are disposed beneath the inductance element are such that a sourceregion of the switching element and a cathode-side region of the diodeare laid out to oppose each other on a semiconductor substrate, whereinat least more than two sets of combination units, each having acombination of switching element and diode with the both regions beingelectrically coupled together, are connected in parallel. Additionally,the booster circuit is designed to have a spirally wired first metalwire for forming the inductance element, a second metal wire connectedto an outer periphery end of the first metal wire for supplying thepower supply voltage, an interlayer connection wire connected to aninner periphery end of the first metal wire while being wired from theinner periphery end toward underlying diffusion layers of the switchingelement and the diode, and a third metal wire for connection between thediffusion layers of the switching element and the diode.

Alternatively, the potential step-down circuit is configurable tocomprise a spirally-wired first metal wiring line for forming theinductance element, an interlayer connection wire connected to an innerperiphery end of the first metal wire while being wired from the innerperiphery end toward underlying diffusion layers of the switchingelement and the diode, a third metal wire for connection between thediffusion layers, and a fourth metal wire connected to an outerperiphery end of the first metal wire for outputting the final outputvoltage thus potentially reduced.

Alternatively the inductance element is arranged to have a first metalwire and an interconnect dielectric film between wiring layers.

In accordance with another further aspect of the invention, a devicestructure is provided which comprises a plurality of semiconductordevices each of which is similar to the above-noted semiconductordevice, wherein these semiconductor devices are laid out to overlap eachother, wherein those inductance elements within neighboringsemiconductor devices are arranged so that the inductance elementswithin the other semiconductor devices are prevented from overlappingeach other in the directions immediately above and below the inductanceelements.

Alternatively, a multi-chip type semiconductor device is provided,wherein a plurality of semiconductor devices are formed on asemiconductor chip, wherein inductance elements of certain semiconductordevices are formed at part of the one half side of the semiconductorchip whereas those inductance elements of the other semiconductordevices neighboring upon the semiconductor devices is formed at part ofthe remaining half side of the chip.

Alternatively, the above-noted semiconductor device is either anonvolatile memory or a nonvolatile memory-embedded microcomputer, whichmay be configured in the form of a flash memory or a flashmemory-embedded microcomputer.

Alternatively, a memory card having the semiconductor device and a CPUis also provided.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a voltage booster circuit of a semiconductordevice in accordance with one embodiment of the present invention;

FIG. 2 is a diagram showing a configuration of a primary booster circuitof the semiconductor device in accordance with this invention;

FIG. 3 is a diagram showing for explanation of an operation example ofthe primary booster circuit of the semiconductor device in accordancewith the invention.

FIG. 4 is a circuit block diagram showing a voltage control means of thesemiconductor device in accordance with the invention.

FIG. 5 is a diagram showing, in block form, a configuration ofduty-ratio setup means along with a duty-ratio generator circuit of thebooster circuit of the semiconductor device in accordance with theinvention;

FIG. 6 is a block diagram showing a configuration of a duty ratiogenerator circuit and duty ratio setup means of the booster circuit ofthe semiconductor device in accordance with the invention.

FIG. 7 is a block diagram showing a configuration of a duty ratiogenerator circuit and duty ratio setup means of the booster circuit ofthe semiconductor device in accordance with the invention;

FIG. 8 is a diagram depicting an element layout and a wiring diagramshowing a first embodiment of an on-chip converter of the semiconductordevice in accordance with the invention;

FIG. 9 is a diagram showing a plan view of a first embodiment of theon-chip converter of the semiconductor device in accordance with theinvention.

FIG. 10 is a diagram depicting an element layout and a wiring diagramshowing a second embodiment of the on-chip converter of thesemiconductor device in accordance with the invention;

FIG. 11 is a diagram showing a cross-section of the second embodiment ofthe on-chip converter of the semiconductor device in accordance with theinvention;

FIG. 12 is a diagram depicting an element layout and a wiring diagramshowing a third embodiment of the onchip converter of the semiconductordevice in accordance with the invention;

FIG. 13 is a diagram showing another configuration example of aninductance element in the third embodiment of the on-chip converter;

FIG. 14 is a diagram depicting an element layout and a wiring diagramshowing a fourth embodiment of the onchip converter of the semiconductordevice in accordance with the invention;

FIG. 15 is a diagram showing a one plane of an on-chip inductanceelement of the semiconductor device in accordance with the invention;

FIGS. 16A to 16C are diagrams each showing a cross-sectional view of thethird embodiment of the onchip converter of the semiconductor device inaccordance with the invention;

FIG. 17 is a graph showing a relationship of an area ratio versus powersupply voltage of booster circuitry of the semiconductor device inaccordance with the invention, along with that of a prior known boostercircuit;

FIG. 18 is a graph showing a relation of area ratio versus operationfrequency of the semiconductor device in accordance with the invention,along with that of a prior art booster circuit;

FIG. 19 is a diagram depicting an element layout and a wiring diagramshowing a fifth embodiment of the on-chip converter of the semiconductordevice in accordance with the invention;

FIG. 20 is a diagram showing clock waveforms during a parallel switchingoperation of inductance elements in the fifth embodiment of the onchipconverter of the semiconductor device in accordance with the invention;

FIG. 21 is a diagram showing another embodiment of the booster circuitof the semiconductor device in accordance with the invention;

FIG. 22 is a diagram showing still another embodiment of the boostercircuit of the semiconductor device in accordance with the invention;

FIG. 23 is a diagram showing a one embodiment of the potential drop-downcircuit of the semiconductor device in accordance with the invention;

FIG. 24 is an element layout and wiring diagram showing the fifthembodiment of the onchip converter of the semiconductor device inaccordance with the invention;

FIG. 25 is a diagram showing a configuration of a microcomputer chipwith built-in flash memory using the onchip converter of the invention;

FIG. 26 is a diagram showing a configuration of a system board using amicrocomputer chip with built-in flash memory using the on-chipconverter of the invention;

FIG. 27 is a diagram showing one embodiment of a multi-chip typesemiconductor device using the semiconductor device in accordance withthe invention;

FIG. 28 is a diagram showing one embodiment of a memory card using thesemiconductor device in accordance with the invention;

FIG. 29 is a diagram showing one exemplary prior art voltage boostercircuit of the type using the charge pump scheme; and

FIG. 30 is a diagram for explanation of prior art gate peripheralcircuitry of a DC-DC converter.

DESCRIPTION OF THE INVENTION

FIG. 1 is a diagram showing a configuration of voltage booster circuitryof a flash memory which uses an on-chip converter embodying theinvention.

While the voltage booster circuit in the flash memory generates aplurality of output voltages to be supplied to an array of memory cells,a part thereof will be explained in this embodiment. A primary boostercircuit 100 receives a power supply voltage 101 as input to the flashmemory. The primary booster circuit 100 has its output to which asecondary booster circuit 200 is connected, for making up a seriesconnection together with those leading up to an Nth booster circuit. Inother words, a serial combination of multiple stages of booster circuitsis provided to thereby constitute a plurality of stages of boostercircuits. The Nth booster circuit 900 at the final stage has a voltagecontrol means 910 which controls an output voltage 902 to be output fromthe final stage, and which is connected to a memory cell array 1000 thatis an internal element. The primary booster circuit 100 at the firststage is a DC-DC converter circuit, which is generally made up of aninductance element 110, a switching element 120, a diode 130, a drivercircuit 140 for driving the gate of such switching element, and anoutput smoothing capacitor 150. The individual one of the secondarybooster circuit 200 to Nth booster circuit 900 is configured from avoltage-increasable DC-DC converter circuit or a charge pump circuit.

Upon receipt of a request for writing or reading data into or from thememory or for erasing it, a voltage-boosting power supply circuit withinthe flash memory starts a voltage boosting operation for supplying apredetermined voltage to the memory.

A basic circuit diagram of the voltage-increasable DC-DC convertercircuit is shown in FIG. 2. FIG. 3 is a waveform diagram of its voltageboosting operation.

Firstly, in response to potential rise-up of an output signal CLK of thedriver circuit 140, the switching element 120 of the primary boostercircuit turns on, causing a current (IL) to flow into the inductanceelement 110. This results in a magnetic energy being stored therein.Next, when the switching element 120 turns off in responding topotential fall-down of CLK (High voltage to Low voltage), a diodecurrent (ID) flows through the diode 130 due to the accumulated magneticenergy in such a way that a current of inductance element flowscontinuously, thereby charging up the output smoothing capacitor 150.

Note here that the diode 130 as used herein is a MOS diode made up of aMOS transistor with its drain and gate coupled together: in thisdescription, a drain-side region coupled to the gate will be referred toas anode, whereas a source-side region is called cathode. Optionally, aSchottky diode or PN-junction diode or the like other than the MOS diodemay be used as the diode 130 while taking into consideration theON-to-OFF recovery characteristics.

The above-noted switching operation will be repeated, causing the inputpower supply voltage to rise in potential. Its behavior is shown in FIG.3, in regard to an output voltage Vx of inductance element 110 and anoutput voltage Vout of primary booster circuit 100. A potentially raisedor “boosted” output voltage Vout becomes an input of the secondarybooster circuit. At this time, the output voltage Vout is given asVin×(Ton+Toff)/Toff, where Ton is the ON time of switching element andToff is its OFF time, under an assumption that magnetic fluxes storedduring the time period Ton are drawn out during the period Toff. Inother words, the voltage boost ratio is determined by a switching dutyratio.

In this embodiment, the switching duty ratio is kept constant and isthen regarded as the voltage boosting ratio, whereby it becomes possibleto reduce the circuit scale of the driver circuit 140.

Additionally, the driver circuit 140 that drives the gate of theswitching element 120 includes a gate voltage booster circuit althoughnot specifically depicted herein. By driving the gate of switchingelement 120 by a voltage higher than the input power supply voltage 101,it becomes possible to shrink the gate width of switching element. Thusit becomes possible to reduce the layout area of such switching elementwhile enabling the switching element to decrease in gate capacitance anddrain junction capacitance, which in turn makes it possible to suppresschargeup losses occurring due to these capacitances. Thus, the voltagebooster circuit 100 is improved in efficiency as a whole. Furthermore,it is also possible to reduce the area required for the layout ofswitching elements, so it is possible to shorten the internal wiringlength thereof. This makes it possible to suppress losses occurring dueto wiring resistances. Although the gate voltage booster circuit in thedriver circuit 140 uses a charge pump circuit, what is required for thedriver circuit is that its output voltage is higher than the input powersupply voltage 101. Owing to this, it becomes possible to permit theboost ratio of the gate voltage booster circuit to be lower than theboost ratio of the entirety. Also note that the load capacitance of thegate voltage booster circuit is the switching element gate capacitanceonly, which is less than the load of the voltage booster circuit 100. Inview of the foregoing, the circuit scale of gate voltage booster circuitis more shrinkable when compared to the case where every booster circuitis realized by a charge pump circuit. Thus it is possible to provide areduced area which allows it to be situated under the inductance element110.

In this embodiment, those behind the primary voltage booster circuit arealso designed so that each booster circuit boosts a voltage with itsunique boost ratio in the case of using a DC-DC converter circuit.Appropriate control is done to provide a prespecified voltage at thefinal stage of Nth booster circuit, which voltage is then supplied to amemory cell or cells. In the case of using charge pump circuits forthose behind the primary voltage booster circuit also, a similar designis employed to allow each booster circuit to boost a voltage with itsfixed boost ratio, when the need arises. Then, control is done toprovide a prespecified voltage at the final stage of Nth boostercircuit, which is then supplied to a memory cell(s).

Optionally, the voltage control is also available by a procedure havingthe steps of controlling to provide a specified voltage at an (N−1)thvoltage booster circuit immediately preceding the final stage, causingthe final-stage Nth booster circuit to perform a boosting operation withits unique boost ratio, and then supplying the resultant voltage to amemory cell(s). With this approach, it becomes possible to reduce thecircuit scale of the driver circuit 140. Alternatively, the voltagecontrol is modifiable to be performed by both the final-stage Nthbooster circuit and the (N−1)th booster circuit in order to attainconflicting requirements—that is, reducing the circuit scale andobtaining a high-accuracy voltage.

According to this invention, letting the primary voltage booster circuitbe a DC-DC converter circuit, it is possible to determine thedrivability of switching elements in such a way as to enable reservationof an inductance current even when the input power supply voltage dropsdown to about 1V or less, which in turn enables achievement of thevoltage rise-up required. More specifically, the intended voltage riseupis achievable as far as it is possible to store in the inductanceelement a magnetic energy greater than the energy required for the loadin a post stage. Additionally, the driver circuit and the voltagecontroller are simplified in configuration, thereby making it possibleto reduce the layout area of the voltage-boost power supply circuitry.

On the contrary, in prior art charge pump circuits, a capacitor is usedto store electrical charge. This capacitor has a one-side terminal, towhich a pulsate bias voltage is applied for transmission of the chargetoward the next step. A diode is provided in each step for avoiding backflow of the charge. A boost voltage corresponding to one step is avoltage equivalent to a difference between the power supply voltage andthe diode's forward drop-down voltage. Accordingly, when the powersupply voltage decreases to about 1V, the diode voltage becomes adominant so that the voltage boosting is hardly achievable.

FIG. 4 is a block diagram showing an exemplary voltage control means 910for controlling the magnitude of an output voltage at the final stage.This voltage control means 910 is arranged to have a serial combinationof multiple gate/drain-coupled MOS diodes 920 while letting a sum oftheir threshold voltages be equal to a predetermined voltage and alsocausing a current flowing when an output voltage of the Nth boostercircuit exceeds a prespecified voltage to become a constant current. Asmoothing capacitor 151 is connected to an output terminal of boostercircuit 900.

When a voltage that is taken out of the series-connected MOS diodes 920exceeds a prespecified voltage, a constant current flows, resulting in acomparator 922 generating a stop signal to thereby avoid a potentialriseup. On the other hand, when the voltage taken out of the MOS diode920 becomes lower than a specified voltage, the comparator 922 gives astart-up signal to an oscillator circuit 904, for controlling thevoltage of the Nth booster circuit 900 so that its output voltage risesup. Note here that although in this embodiment the voltage controller isprovided at the final stage of booster circuitry, such controller may beprovided at a location near the final stage—for example, at its frontstage—while causing the final stage to have a constant voltage boostratio.

In this way, the constant current is converted into an appropriateconstant voltage, which is then compared by the comparator 922 with areference voltage. This causes the oscillator circuit 904's outputvoltage being input to the Nth voltage booster circuit 900 to turn onand off, thereby obtaining a constant voltage with a specified potentiallevel. Accordingly, reduction of the circuit scale becomes possible bycontrolling only an output voltage of the final stage while roughlyhandling an intermediate voltage(s) with a fixed boost ratio(s).

Note here that the circuit scale reduction of the gate driver circuit140 is enabled by making the switching duty ratio constant to provide afixed voltage boost ratio. The reason of this is as follows. Forcomparison purposes only, an explanation will first be given of a priorart control scheme of traditionally configured DC-DC converter circuitryfor potentially raising an input voltage 6101 shown in FIG. 30 up to anoutput voltage 6102.

The above-noted gate driver circuit 140 corresponds to a gate controlcircuit 6140. First, the output voltage 6102 is fed back via a filter6141. Then, an error between it and an output of a reference voltagegenerator circuit 6142 is amplified by an error amplifier 6143.

Thereafter, an output of the error amplifier 6143 and an output of atriangle wave generator circuit 6144 are passed to a comparator 6145,which compares them to determine the ON or OFF of the switching element120 and then send a signal to a gate driver circuit 6146. The gatedriver circuit 6146 causes the switching element 120 to vary in ON timeratio, thereby constantly retaining the output voltage.

This requires the use of a circuit block including the filter 6141 forthe feedback use, reference voltage generator circuit 6142, erroramplifier 6143, triangle-wave generator circuit 6144, comparator 6145and others. By contrast, in the case of this invention, the DC-DCconverter circuit per se does not perform any feedback of an outputvoltage; instead, let the switching element 120 operate in accordancewith a preset switching duty ratio.

Therefore, the above-noted feedback loop configuration is no longerrequired, and similar results are attainable only by the gate drivercircuit along with a circuit for generating a fixed switching dutyratio. Thus, its circuit scale can be reduced.

It is also possible to achieve high-frequency operations because thegate driver circuit 140 becomes simpler in configuration. As a result,the inductance can be selected to have a small value, thereby enablingreduction of the occupation area of the switching element 120.

Although the switching frequency and switching duty ratio are littlevariable due to deviations in the manufacture of those elements makingup the gate driver circuit 140, the intended voltage boosting isattainable even though the gate driver circuit 140 is reduced in scale.

In other words, even in case a second voltage booster circuit 200 at thenext stage is a charge pump circuit, what is required is merely that acertain voltage exceeding the barrier of a forward drop-down voltage ofa diode can be output from the first-stage booster circuit 100—in thiscase, the voltage boost ratio determinable by the switching duty ratiomay be kept low in accuracy. Additionally, although the scale of thegate driver circuit 140 becomes larger, it is also possible to use acontrol circuit which stabilizes the switching duty ratio.

Furthermore, there may be provided the means for permitting setup of theswitching duty ratio from the outside not only during designing worksbut also during manufacture and operation. Hereinafter, one example ofthe duty ratio generating circuit and the duty ratio setting means willbe shown in FIGS. 5 to 7.

FIG. 5 is a block diagram showing the duty ratio generator circuit usinga counter and a comparator. An operation of this circuit is as follows.An oscillator 7001 outputs a rectangle wave signal 7002. A counter 7003counts up its pulse number and generates a counter output 7004, which iscompared by a comparator 7005 to a digital value 7008 that was set by aduty ratio setup unit 7007. Thus a switching signal 7006 with a desiredduty ratio is generated.

The switching signal 7006 is input to the gate driver circuit 140 andthen amplified to thereby make it possible to drive the switchingelement 120 and thereafter drive the gate. In case the counter 7003 is acounter with a set of cycle value and switch-on time value and a periodbeing fixed, the set value 7008 may be only the value of the switch-onor off time. In this way, it becomes possible to obtain a desiredswitching duty ratio even where the duty ratio of the oscillator 7001 isout of management.

Although the explanation was given with reference to the drawing inwhich the oscillator 7001 for generating the rectangle wave 7002 is laidout as part of the duty ratio generator circuit, when using a pluralityof DC-DC converter booster circuits with different boost ratios, anoscillator may be used in common; alternatively, a clock signal beingsupplied from the outside of an LSI is employable as the rectangle wave7002.

Optionally, oscillators and duty ratio generator circuits may beprovided in all the gate drive circuits of respective voltage boostercircuits. Alternatively, it is also possible to make the oscillatorcommon to thereby permit direct input to the booster circuit of thecharge pump scheme while individually disposing duty ratio generatorcircuits in the booster circuits of the DC-DC converter circuit scheme.Obviously, those booster circuits with the same duty ratio may bedesigned to share a duty ratio generator circuit.

FIG. 6 is a block diagram showing a duty ratio generator circuit usingan oscillator with a triangle wave output. Based on a value 7008 as setby a duty ratio setup unit 7007, determine a threshold value 7110, whichis an output of a threshold value generating circuit 7109. A comparator7105 compares the threshold value 7110 to an instantaneous value of thetriangle wave from a triangle generator 7101, thereby generating aswitching signal 7006 that has a desired duty ratio.

An example of the oscillator circuit which can modify the duty ratio ofan oscillator per se is shown in FIG. 7. An oscillator 7501 includes aduty ratio setup unit 7507 having two sets of CR delay time constantvalues (i.e., 7507 a*7507 c and 7507 b*7507 d).

Letting such ratio be t1:t2, the duty ratio of a switching signal 7006is given by t1:t1+t2. The duty ratio setup unit 7507 is such that aresistor 7507 a is adjustable, wherein the other electrostaticcapacitors 7507 c, 7507 d have the same fixed value, and a resistor 7507b also is fixed.

As the duty ratio setup unit 7007 described in FIGS. 6-7, there are twomethods which follow: a method for retaining the set value 7008 in a waydepending upon the presence or absence of a wiring connection due to afuse, a wiring mask option, a mask option of contact layout, or aterminal connection option at the time of parts-mounding or the like;and, a method of holding the set value by using a rewritable memorydevice such as a nonvolatile memory, a register or else. In the case ofusing the register, it is required that the value be defined uponpower-up. To do this, there is considered an arrangement for reading theset value out of a nonvolatile memory or equivalents thereto.

While it is also possible to directly change the resistance value orcapacitance value by modifying the wiring connection such as fuses orwiring options or the like, the set value may be provided indirectly.Adversely, in the case of using for the duty ratio setup a value storingmeans such as a nonvolatile memory or a register, a method may also beavailable for change-over of a switch element in such a manner as tomodify the resistance value or capacitance value based on such thevalue.

The prior art DC-DC converter-used comparator shown in FIG. 30 isrequired to make up a differential amplifier for the voltage comparisonpurpose. However, the counter-used comparator of the duty ratio setupscheme embodying the invention shown in FIG. 5 is configurable by logiccircuitry and thus is less in circuit area than the differential amp.Although in FIG. 6 such differential amp becomes necessary, phasedesigns become easier since the duty ratio is directly set up withoutconstituting any feedback control loop.

Although in the embodiments shown in FIGS. 5 to 7 the voltage boostratio is indirectly determined by the switching duty ratio, there is anapproach that a block (not shown) for converting a boost ratio into aduty ratio is provided to thereby use the boost ratio as the set value.

By letting the boost ratio be setup-variable in this way, in cases wherean input voltage to a memory LSI is 3V during high-speed operations anddrops down at 1V during low power consumption operations, it ispossible, by changing the switching duty ratio within the LSI inaccordance with a present operation mode, to deal with any change ininput voltage while using a simple circuit configuration. It is alsopossible to fabricate as the same chip a product of the type capable ofoperating at high speeds and another one operable at low speeds whileoffering low power consumption and then divide it into different typesof chip products by modifying an internal resistor(s) at the time ofshipment.

According to the invention, designing the first-stage voltage boostercircuit as a DC-DC converter circuit permits determination of thedrivability of switching element 120 in such a way that an inductancecurrent is obtainable even when an input power supply voltage decreasesto about 1V, whereby the voltage boosting becomes possible. In otherwords, the boosting is enabled if it is possible to store in theinductance element 110 a magnetic energy greater than the energyrequired for the load of a post stage.

In addition, the driver circuit and voltage controller also aresimplified, thereby reducing the layout area of the voltage-boost powersupply circuit. In contrast, the charge pump circuit is such that chargeis stored in a capacitor having terminals, one of which is applied apulsate bias voltage for transferring the charge toward the next step. Adiode for preventing the reverse flow of a current is required for eachstep.

A boosted voltage corresponding to one step is a voltage equivalent to adifference between the power supply voltage and the diode's forward dropvoltage. Thus, when the power supply voltage drops down at about 1V, thediode voltage becomes a dominant, resulting in any intended voltageboost becoming almost impossible.

FIG. 8 shows a first embodiment of the on-chip converter of thisinvention. This diagram depicts the layout of an inductance element 110making up the on-chip converter and its peripheral elements including aswitching element 120 and diode 130, along with a connectionrelationship thereof, wherein a formation area of the switching element120 is designated by M whereas that of the diode 130 is denoted by D. Inaddition, a planar configuration of the first embodiment of the on-chipconverter of the invention is shown in FIG. 9. As shown in FIG. 9, theconverter is formed in a partial area of a semiconductor chip, fordriving an element within the chip (for example, a flash memory element,not shown) after having boosted an input power supply voltage 101 by thecircuit shown in FIG. 1 (only a converter part is shown in FIG. 9).

A metal wiring unit 111 which is a first metal wire of the inductanceelement 110 is obtained by causing either a signal wiring line of aflash memory element within the semiconductor chip of FIG. 9 or a metalwire for use as a power supply wire—in the flash memory element, a metalwire at the second layer for use as a signal wire—to have a spiralshape, wherein a core part of the inductance element 110 is formed of adielectric film lying between wiring layers and a protective dielectricfilm.

Traditionally in the case of forming inductance elements within a chip,the resultant series resistance has been reduced by especially adding aprocess for wiring a thick film with a thickness of several μm or bybonding together those fabricated by separate processes. In thisinvention, as has been described previously, the inductance element 110is fabricated in the on-chip fashion without modifying the wiringprocess of the flash memory, for example.

Details of the structure will be described later with reference to FIGS.16(a) to 16(c) in the explanation of a parallel-connection typeinductance.

A second metal wiring line for supplying the input power supply voltage101 is connected to an outer peripheral portion of a metal wiring unit111 of the inductance element 110; an interlayer connection wiring line181 extending downward from an inner periphery of the metal wiring unit111 to the substrate side is connected to a first-layer metal wire m1,which is a third metal wire for connecting together diffusion layers(not shown) of switching element 120 and diode 130. The metal wire m1consists of metal wire components “m1 a” and “m1 b,” wherein m1 aextends in a one direction to almost the same extent as one side of theinductance element for subdivision of the formation area M of theswitching element 120 and the formation area D of diode 130 with thedirection as a boundary, whereas m1 b extends from a plurality ofportions of m1 a in a direction perpendicular to m1 a and is thenconnected to the diffusion layers (not shown) of the switching element120 and diode 130. For brevity purposes, only those metal wires betweenthe switching element 120 and diode 130 and the inductance element 110are shown in FIGS. 8-9, with the other wires omitted herein (the samegoes with the following drawings expect as otherwise explained to thecontrary).

Also note that while the shape of the metal wiring unit 111 of theinductance element 110 is a rectangle in FIG. 8 for simplicity purposes,it may alternatively be designed to have other polygons, such as anoctagon or a sixteen-angled polygon. The same goes with the embodimentsbelow.

As in this embodiment, it is possible to lessen the inter-element wiringresistance and parasitic inductance by providing the switching element120 and diode 130 immediately beneath the inductance element 110 andletting the interlayer connection wire 181 extending downward from theinner periphery of the metal wiring unit 111 to the semiconductorsubstrate side be connected to the first-layer metal wire m1 forconnection between the diffusion layers of the switching element 120 anddiode 130. Thus it is possible to downsize the on-chip converter withoutlowering the power supply efficiency. This also makes it possible toreduce noises during switching operations.

See FIG. 10, which shows a second embodiment of the on-chip converter ofthe invention. This diagram depicts the layout of an inductance element110 making up the on-chip converter and its peripheral elementsincluding a switching element 120 and diode 130, along with a connectionrelationship thereof, wherein a formation area of the switching element120 is designated by M whereas that of the diode 130 is denoted by D.

FIG. 11 is a diagram showing a cross-section of the second embodiment ofthe on-chip converter of the invention. In FIG. 11, reference numeral1200 indicates a well diffusion layer in which more than one MOStransistor (switching element 120) and MOS diode (diode 130) are to beformed; 120D and 120S denote those diffusion layers constituting thedrain and source regions of each switching element, respectively; and,130A and 130K are diffusion layers forming the anode and cathode regionsof each diode, respectively.

In the formation area M of the switching element 120, two transistors M1and M2 are provided while sharing a diffusion layer 120S for forming asource region, wherein a first-layer (metal) wiring line that isconnected to the diffusion layer 120S via a contact wire is a GND wirebeing coupled to ground potential. In the formation area D of diode 130,two transistors D1 and D2 are provided while sharing a diffusion layer130K for forming a cathode region, wherein a first-layer (metal) wiringline that is connected to the diffusion layer 130K via a contact wire isa Vout wire, which becomes an output potential of the converter circuit.A wire G included in the gate wiring lines is a gate portion of theswitching element 120, while a wire that is connected to the diffusionlayer 120D (130A) via a contact wire and first-layer (metal) wire is agate portion of the MOS diode 130.

The switching element 120 and diode 130 are each subdivided into aplurality of portions. The drain region of switching element 120 and theanode region of diode 130 are laid out to oppose each other. The bothregions are formed in the same diffusion layer 120D (130A). M1 and D2 orM2 and D1 are called a combination unit. The switching element 120 anddiode 130 are arranged so that a plurality sets of such combinationunits are connected in parallel.

With such an arrangement, the wiring distance between the switchingelement 120 and diode 130 becomes shortened when compared to the firstembodiment shown in FIG. 8, resulting in likewise decreases in wiringresistance and parasitic inductance. Thus it is possible to downsize theinductance element and also reduce switching noises.

As has been stated above, it is possible to lessen the inter-elementwiring resistance and parasitic inductance by providing the switchingelement 120 and diode 130 immediately under the inductance element 110and letting the interlayer connection wire 181 extending downward fromthe outer periphery of the metal wiring unit 111 toward the substrateside be connected to the first-layer metal wire m1 for connectionbetween the diffusion layers of the switching element 120 and diode 130.Thus it is possible to downsize the on-chip converter without loweringthe power supply efficiency. This also makes it possible to reducenoises during switching operations.

A third embodiment of the on-chip converter of the invention is shown inFIG. 12. This embodiment is such that a plurality of metal wiring unitsare provided, each of which is similar to that of the inductance element110 shown in FIG. 8. As stated in the previous embodiment (FIG. 8),metal wiring units 111, 112 are formed by using, with no changes,certain ones of metal wires for use as signal wires or power supplywires of a flash memory element within a semiconductor chip—in the flashmemory element, second- and third-layer metal wires for use as signaland power supply wires, respectively.

Very importantly, the metal wiring units 111, 112 of spiral-shapedinductance elements with the same planar shape at a plurality ofdifferent wiring layers are formed so that these overlap each otherwhile permitting penetration of magnetic fluxes therebetween and alsoletting the magnetic fluxes occurring in the case of flow of a currenttherein be the same in direction. In the case of parallel connection ofinductance elements of a single wiring layer in a layout which preventsmutual interference of the magnetic fluxes, the resultant resistancebecomes equal to 1/k (where, k is the number of parallel-connectedinductance elements); however, the inductance value also decreases to1/k. By such superposition while allowing the magnetic fluxes tomutually penetrate in the same direction, it is possible to make theinductance value almost equal to the inductance element per layer whileletting the resistance be 1/k. Whereby, it becomes possible tomicro-fabricate and integrate those inductance elements of lowresistance on a chip (although not specifically depicted, respectivelayers may be connected together at their equal-potential portions byusing through-going holes or the like).

The metal wiring units 111-112 that form the parallel-connectedinductance elements are not always formed to have the same shape andsame size; for example, the shape of 111 may be modified to a rectanglewhereas the shape of 112 is altered to an octagon as far as the mutualpenetration of magnetic fluxes is available. Additionally as shown inFIG. 13, unless spiral center points 111 a, 112 a of 111 and 112 aremutually offset from the other spiral-shaped metal wiring units uponprojection of 111 onto 112, the center points may not necessarily beidentical to each other.

It is also possible, by the use of such multilayer-wiredparallel-connected inductance elements, to suppress an increase inresistance otherwise occurring due to skin effects when the switchingelement 120 is designed to perform high-speed operations. In order tofurther minimize the inductance element, high-frequency switching isrequired. However, skin effects appear when the frequency exceeds 20MHz, resulting in current concentration only at the surface of aconductor. In this case, even when low-resistance inductance elementsare designed using the wiring with a thickness of several μm, thecurrent can hardly flow in an entirety of the conductor cross-section sothat the resistance increases in value. But, in the inductance elementmade up of a plurality of parallel-coupled wiring layers, its conductorsurface area is greater than that of thick-film wires even in case atotal cross-sectional area is the same. Thus there is an advantage thatan increase in resistance due to skin effects is suppressed orminimized.

A fourth embodiment of the on-chip converter of the invention is shownin FIG. 14. This embodiment is the one that forms the metal wiring units111 and 112 of FIG. 12 by a third-layer and four-layer wiring linesrespectively while using the first- and second-layer wires to form ametal wire m1 for connection between the diffusion layers (not shown) aswitching element 120 and diode 130. This is advantageous for reducingthe wiring resistance between the metal wiring units and the switchingelement and/or diode when the first-layer metal wires are relativelylarge in sheet resistance.

A plan view of the metal wiring unit 111 of the inductance element shownin FIG. 12 is shown in FIG. 15. Its cross-sectional views along lineA-A′, B-B′ and C-C′ are shown in FIGS. 16(a) to 16(c), respectively.

In FIG. 15, reference characters 180 a to 189 a indicate connectionnodes of interlayer connection wires 180-189 and metal wiring unit 111,respectively.

In each of FIGS. 16(a)-16(c), the inductance element 110 is aparallel-connection type inductance element which is made up of second-and third-layer metal wires, an inter-wiring layer dielectric filmprovided between these layers, and a protective insulating film. Morespecifically, the illustrated example is an inductance of the typehaving a parallel connection of a plurality of layers structured fromthe metal wires and the inter-wire dielectric film. The inductanceelement-forming metal wires are spiral-shaped wiring lines consisting ofa plurality of metal wiring layers such as shown in FIG. 12 and FIG. 15,wherein an input power supply voltage 101 is supplied to the outerperiphery of such spiral wiring structure. At each spiral wire, outerperipheral portions are connected together by an interlayer connectionwiring line 180, wherein an interlayer connection wire 181 extendingdownward from the inner periphery toward the substrate side intersectsthe first-layer metal wire m1 a (see FIG. 16(a)). The metal wire m1 aextends in a B-B′ direction by a degree that is substantially the sameas one side of inductance element (see FIG. 16(b)). With the metal wirem1 a as a boundary, the formation area M of switching element 120 (120 aof FIG. 16) and the formation area D of diode 130 (130 a of FIG. 16) aredivided so that a metal wire m1 b extends from multiple portions of m1 ain a C-C′ direction (see FIG. 12) while letting it be connected to thediffusion layers (not shown) of switching element 120 and diode 130(FIG. 16(c)).

FIG. 17 is a graph showing, regarding the voltage booster circuitembodying this invention and one prior art booster circuit, therelationship of an area ratio versus power supply voltage when primarilyboosting a voltage to 7V. In the prior art booster circuit using acharge pump circuit, its circuit area increases with a decrease in powersupply voltage, resulting in a rapid increase of area when the powersupply voltage is less than or equal to 2V. In contrast, using thebooster circuit of the invention results in no appreciable increase incircuit area—the area becomes smaller than the prior art circuit schemeat about 2.5V. The reason for the prior art booster circuit's arearapidly becoming larger when the supply voltage is at 2V or less is asfollows: in the charge pump circuit, a boosted voltage per pump becomesa voltage equivalent to a difference between the supply voltage and thedrop-down voltage of MOS diode (about 1V or more under the influence ofa substrate bias) so that the stage number of charge pump circuitsrequired for the intended voltage boosting increases. In contrast, theinvention is such that in case a primary booster circuit output voltage102 is about 7V, the intended voltage boosting is achievable by a singlestage, so it is almost free from the influence from the MOS diode dropvoltage.

FIG. 18 is a graph showing, as for the voltage booster circuit of thisinvention and prior art booster circuit, the relationship of an arearatio versus operation frequency when primarily boosting a voltage to7V. When the operation frequency of booster circuit becomes about 10 MHzor higher, the booster circuit of the invention is less in size than theprior art booster circuit. The reason of this is as follows. Whereas thesize of a capacitor that almost determines the size of charge pump is ininverse proportion to the pump's changeover operation frequency, thesize of inductance element that almost determines the size of DC-DCconverter circuit is in inverse proportion to the square of switchingfrequency.

A fifth embodiment of the on-chip converter of the invention is shown inFIG. 19. Although the layout of switching element 120 and diode 130 isnot depicted for simplicity purposes only, four circuit units are laidout, each of which is similar in configuration to the converter shown inFIG. 12 with its size made smaller. The maximum consumed current andaverage current of the DC-DC converter circuit shown in FIG. 2 aredeterminable by an inductance current IL: the maximum current becomeslarger and is about two times greater than the average current. Due tothis, the load of a flash memory relative to an input power supplyincreases in some cases.

To avoid this risk, as shown in FIG. 19, the inductance element 110 ofFIG. 12 is divided into a plurality of sets (in FIG. 19, four sets 110a, 110 b, 110 c and 10 d) in such a manner that its total inductancevalue becomes the same, while providing four switching elements forcausing them to perform operations in parallel with a difference inswitching phase as shown in FIG. 20, thereby reducing a peak of a totalof inductance currents.

Suppose that the area of a single inductance element is set at 1/k. Inthe case of a k-parallel operation, the average current becomes the sameas that prior to k division when letting the switching frequency be(k³)^(1/2) times. The maximum current of each phase becomes 1/k, and itssum becomes less than 1; thus, it becomes possible to reduce the totalmaximum current. Furthermore, when performing the parallel operationwith the phase of each switching be offset by 1/k of the cycle orperiod, it is possible to minimize a total of inductance currents, whichin turn makes it possible to reduce the maximum current.

Although the relationship of the voltage boost ratio and the switchingduty ratio has been stated supra, when operating while letting thisboost ratio (=an inverse number of the switching duty ratio) and thebooster circuit parallel division number be the same and also providinga phase difference to ensure equal division of the switching period,ripples of the total current of each phase disappear whereby it ispossible to permit the average current and the total maximum current tobe almost identical to each other. Additionally, in the case of suchdivision, the inductance element layout increases in flexibility. Forexample, the layout is enabled not only for quadrate areas but also forrectangular areas.

FIG. 21 shows the embodiment of FIG. 1 in the case of N=2, with alimiter 103 being disposed at the output of first-stage voltage boostercircuit 100. In this case, the voltage boosting is pre-advanced to anintermediate stage in preparation for startup of an operation of thesecond-stage booster circuit 200. This enables acceleration of thevoltage boosting operation as a whole, resulting in an improvement inmemory access speed. Note that limiters 103, 203 used herein may bedesigned to employ the same circuit scheme as that explained as oneexample of the voltage control means 910 of FIG. 1.

FIG. 22 is a diagram showing a configuration of internal voltageboosting circuitry of a flash memory, which is another embodiment of theinvention. While the flash memory includes its internal power supplyunit with voltage boosting ability which outputs a plurality of voltagesfor supplement to a memory cell or cells, part of it will be explainedin this embodiment. An input power supply voltage 5101 to the flashmemory is input to a first-stage voltage booster circuit 5100.

A second-stage voltage booster circuit 5200 is connected to an output ofthe first-stage booster circuit 5100; similarly, those up to anNth-stage booster circuit 5900 are sequentially connected in series. TheNth-stage booster circuit 5900 has a voltage control means 5910 forcontrol of its output voltage, which in turn is connected to a memorycell array 1000. The first-stage booster circuit 5100 is a charge pumpcircuit, while the second-stage booster circuit 5200 is formed of aDC-DC converter circuit.

Although not depicted herein, third-stage to Nth-stage booster circuits900 are each configurable from a voltage-increasable DC-DC convertercircuit or a charge pump circuit. In case an input power supply voltageVin is potentially raised up to “a” times by using a charge pump circuitfor the first-stage booster circuit, an input maximum current Iin2 ofthe second-stage booster circuit is given as Iin2=a*Vin/Rdc, where Rdcis the current resistance of an inductance element and switchingelement.

Letting the inductance value be L, the storable energy is represented by½L*Iin2*Iin2, so the storing energy is square times greater than “a”when compared to the case of directly supplying the input power supplyvoltage to the DC-DC converter circuit. For this reason, the first-stagebooster circuit is designed using a charge pump circuit while lettingthe second-stage booster circuit be a DC-DC converter circuit, therebyenabling arrangement of voltage booster circuitry with enhancedefficiency.

It should be noted that when the first-stage booster circuit is madehigher in voltage boost ratio than the second-stage booster circuit, theresulting area will possibly increase due to an increase in scale ofcharge pump circuits. To avoid this risk, it is required that thesecond-stage booster circuit be greater in boost ratio than thefirst-stage booster circuit.

An embodiment of a voltage drop circuit using the on-chip converter ofthis invention is shown in FIG. 23. This converter circuit is configuredfrom an inductance element 110, switching element 121, diode 131,switching element gate driving circuit 141, control circuit 142 forcontrol of an output voltage, and output-smoothing capacitor 151. A highvoltage 1010 being input to this converter circuit will be output as aprespecified low voltage 1020.

While the onchip converter-forming inductance element 110 and itsassociated switching element 121 and diode 131 are almost similar, inlayout and wiring along with planar and sectional configurations, tothose shown in FIGS. 8, 10, 12 and 14 and FIGS. 9, 11 and 16(a)-16(c),except for the polarities of elements, the metal wiring unit 111 ofinductance element 110 is connected to a fourth metal wire for output ofa potentially reduced voltage, rather than the wiring line for supplyingthe input power supply voltage 101.

Additionally, in the case of using an arrangement with a parallelconnection of multiple sets of combination units of switching elements121 and diodes 131 in a similar manner to the configuration shown inFIG. 11, these combination units are disposed on a semiconductor chip sothat the source region of a switching element and the cathode region ofa diode oppose each other while letting the both regions be electricallyconnected together.

It is noted that the voltage drop circuit of this embodiment may bearranged to have a plurality of stages as in the voltage booster circuit100, 200, 900 shown in FIG. 1.

In short, a semiconductor device is configurable, which permits an inputvoltage to be potentially dropped down by a primary voltage drop circuitor a group of multiple stages of voltage drop circuits each using it,and which has a voltage control unit for controlling a final droppedoutput voltage to be output from a voltage drop circuit at the finalstage.

FIG. 25 shows a configuration of a microcomputer with a built-in flashmemory using the onchip DC-DC converter of this invention. The flashmemory-embedded microcomputer 300 is generally made up of a CPU 310,flash memory 320, RAM 330, and I/O unit 340. The I/O unit 340 includes aserial I/O, programmable input/output port, analog-to-digital converter(ADC), and digital-to-analog converter (DAC) and others. The flashmemory 320 uses the booster circuit shown in FIG. 1 and the onchipconverter shown in FIG. 4, by way of example.

FIG. 26 shows a configuration of a system board 3000 having the flashmemory-embedded microcomputer 300 using the onchip converter of theinvention. The system board 3000 has, other than the flashmemory-embedded microcomputer 300, an LSI for the application systemuse, which is an object to be controlled by the microcomputer, andbuilt-in discrete components 3100. The system board 3000 is connected bya serial I/F or else to a personal computer (PC) 3200 so that anapplication program of the application system is sent from the PC 3200and then written into the built-in flash memory 320 of the flashmemory-embedded microcomputer 300.

The flash memory-embedded microcomputer 300 indicated in this embodimentis widely adaptable for use as an in-vehicle microcomputer forperforming engine control and body control operations, a plasma displaypanel (PDP), and a system-control microcomputer such as DVD-relatedequipment.

FIG. 27 is a diagram showing an internal block arrangement of two typesof semiconductor devices 10 and 20 to be used during packaging with aplurality of semiconductor devices of the invention being stacked overone another. FIG. 28 schematically shows a cross-sectional structure ofa multi-chip type semiconductor device with the semiconductor devices 10and 20 being stacked into the form of a card. In FIG. 27, numeral 10designates a first semiconductor device; 20 denotes a secondsemiconductor device; 11, 21 is a memory cell area; 12, 22 is aperipheral circuit area; 1110, 1120 is a voltage booster circuit areawhich includes the primary booster circuit 100 of the invention statedsupra. Here, the semiconductor device 20 has a configuration that isobtained by mirror-like inversion of the element layout of thesemiconductor device 10. Owing to this, the inductance element 110residing within the booster circuit area 1110 of semiconductor device 10is provided in the left-half area of a chip, whereas the inductanceelement 110 within the booster circuit area 1120 of semiconductor device20 is provided in the right-half area of the chip. In FIG. 28, numeral40 denotes a memory card; 30 is a CPU; 31, bonding wires forinterconnection between electrode pads of the first semiconductor device10 and second semiconductor device 20. The semiconductor devices 10, 20are stacked over each other so that their a-a′ and b-b′ cross-sectionseach become the cross-section of FIG. 28. For example in FIG. 28, a partof the booster circuit area 1110 of semiconductor device 10, which is atthe deep end of the drawing sheet, becomes the peripheral circuit area12.

An arrangement of a memory card employing the memory card using thevoltage booster circuitry of the invention will be described below.

This invention provides an arrangement comprising a plurality ofsemiconductor devices and a controller CPU, each of which devicesincludes a semiconductor device comprising a plurality of stages ofvoltage booster circuits for potentially raising a power supply voltageup to a predetermined final output voltage, a voltage control unitconnected to a voltage booster circuit near its final stage for controlof a final output voltage, and more than one internal element to whichthe final output voltage is supplied, wherein a first stage of voltagebooster circuit includes a converter circuit having an inductanceelement, a switching element, a diode and a driver circuit for drivingthe switching element, and wherein the switching element and diode arepartly laid out to underlie the inductance element. Each semiconductordevice is connected by bonding wires to the CPU and is disposed so thatit is superposed with the others. Inductance elements within neighboringsemiconductor devices are arranged so that those inductance elementswithin the other semiconductor devices are disposed not to mutuallyoverlap in the direction immediately above and beneath the inductanceelements.

In the case of packaging of the plural semiconductor devices in astacked manner, it can sometimes happen that the operations becomeunstable due to the interference of magnetic fluxes as created frominductors between neighboring semiconductor devices. If this is thecase, let the first and second semiconductor devices such as shown inFIG. 27 be superposed together as shown in FIG. 28, whereby theinductance elements do not overlap each other in the up-down directions.Thus the interference of magnetic fluxes no longer take place.

It should be noted that although in the above embodiment thesemiconductor device embodying this invention has been explained bytaking a flash memory as an example, the invention may also be appliedto any other devices that are arranged so that a voltage higher than thepower supply voltage is generated by internal circuitry for drivinginternal elements. The invention is applicable to semiconductor devicesother than the flash memory and other types of memories—for example, asemiconductor device such as a microprocessor/controller. In this case,there is an advantage such as providing the drivability with the voltageof a single dry battery.

Optionally in FIG. 28, a memory such as SRAM or DRAM may be superposedtogether with the flash memory.

Furthermore, according to this invention, it is possible to lower thepower supply voltage to about 1V while enabling reduction of theparts-mount area. Accordingly, when applying the semiconductor device ormulti-chip type semiconductor device of the invention to mobileelectronic equipment such as cellular phones and PDAs or the like, itbecomes possible to achieve low power consumption while at the same timedownsizing the equipment at low assembly costs.

The reference characters as used in the description indicate thefollowing parts or components.

10 . . . First Semiconductor Device, 11, 21 . . . Memory Cell Area, 12,22 . . . Peripheral Circuit Area, 20 . . . Second Semiconductor Device,30 . . . CPU, 40 . . . Memory Card, 100 . . . Primary Voltage BoosterCircuit, 101 . . . Input Power Supply Voltage, 102 . . . Output Voltageof Primary Booster Circuit, 103, 203 . . . Limiter, 104, 204 . . .Oscillator, 110 . . . Inductance, 120, 121 . . . Switching Element, 130,131, 170 . . . Diode, 140, 141 . . . Switching Element Gate DriverCircuit, 142 . . . Control Circuit, 150, 151 . . . Output SmoothingCapacitor, 160 . . . Capacitor, 200 . . . Secondary Voltage BoosterCircuit, 900 . . . Nth Voltage Booster Circuit, 902 . . . OutputVoltage, 910 . . . Voltage Control Unit, 1000 . . . Memory Cell Array,1110, 1120 . . . Voltage Booster Circuit Area.

INDUSTRIAL APPLICABILITY

In the present invention, it is possible to provide a semiconductordevice capable of achieving miniaturization without having to reduce theefficiency of power supply while enabling reduction of switching noises.It is also possible to provide a memory card using the same.

1. A semiconductor device comprising a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a predetermined final output voltage, an output voltage control means connected to a voltage booster circuit adjacent to a final stage of said voltage booster circuits, and an internal element to which an output of said voltage booster circuits is supplied, wherein a first stage voltage booster circuit of said voltage booster circuits for raising the power supply voltage up to a primary voltage is formed of a converter circuit including an inductance element, a switching element and a diode, wherein voltage booster circuits in back of the first stage for raising said primary voltage up to the predetermined final voltage are each configured from a charge pump circuit including a capacitance element and a diode or a converter circuit including an inductance element, a switching element and a diode, wherein the inductance element and the switching element plus the diode making up said voltage booster circuit as well as said output voltage control means and said internal element are formed on a semiconductor substrate, and wherein said output voltage control means controls the voltage booster circuit near said final stage and supplies its output to said internal element.
 2. A semiconductor device comprising a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a predetermined final output voltage, an output voltage control means connected to a voltage booster circuit near a final stage of said voltage booster circuits, and an internal element to which an output of said voltage booster circuits is supplied, wherein a first stage voltage booster circuit of said voltage booster circuits for raising the power supply voltage up to a primary voltage is formed of a charge pump circuit including a capacitance element and a diode, wherein any one of voltage boost stages in back of the first stage for raising said primary voltage up to the predetermined final voltage is configured from a converter circuit including an inductance element, a switching element and a diode, wherein the inductance element and the switching element plus the diode making up said voltage booster circuit as well as said output voltage control means and said internal element are formed on a semiconductor substrate, and wherein said output voltage control means controls the voltage booster circuit near said final stage and supplies its output to said internal element.
 3. The semiconductor device according to claim 2, wherein a voltage boost ratio of said first stage voltage booster circuit is less than that of a converter circuit at a succeeding location of said first stage.
 4. The semiconductor device according to claim 1, wherein said power supply voltage is less than or equal to 2.5V.
 5. The semiconductor device according to claim 1, wherein at least one converter circuit of said converter circuits is such that its voltage boost ratio is maintained at a preset value during a voltage boosting operation.
 6. The semiconductor device according to claim 1, further comprising means for causing, in at least one converter circuit of said converter circuits, a voltage boost ratio to be retained at a preset value during a voltage boost operation and for arbitrarily setting the voltage boost ratio.
 7. The semiconductor device according to claim 1, wherein at least one converter circuit of said converter circuits is such that a switching duty ratio is kept at a preset value during a voltage boost operation.
 8. The semiconductor device according to claim 1, wherein at least one converter circuit of said converter circuits is 10 MHz or more in its switching frequency.
 9. The semiconductor device according to claim 1, wherein said inductance element is a parallel connection type inductance element consisting essentially of multilayered metal wiring layers and a dielectric film provided between the wiring layers, with said multilayered metal wiring layers being connected in parallel.
 10. The semiconductor device according to claim 9, wherein a metal wire forming said inductance element is a spiral-shaped wiring line, wherein said spiral-shaped wiring line has an outer peripheral end connected to a wire for supplying said power supply voltage and also has an inner peripheral end connected via a metal wire to a diffusion layer of said switching element as formed in an element area beneath an inductance element.
 11. The semiconductor device according to claim 1, wherein said internal element operable upon application of a voltage higher than the power supply voltage is a non-volatile memory.
 12. A memory card using the semiconductor device according to claim
 1. 13. A semiconductor device comprising: a plurality of stages of voltage booster circuits for raising a power supply voltage up to a prespecified final output voltage; a voltage control unit connected to more than one voltage booster circuit within said plurality of stages of voltage booster circuits for controlling an output voltage near a final stage; and an internal element to which the final output voltage is supplied from said plurality of stages of voltage booster circuits, wherein a converter circuit provided within said plurality of stages of voltage booster circuits at least has an inductance element, a switching element, a diode and a driver circuit for driving said switching element, and said inductance element of said converter circuit at least includes a metal wire to be formed at the same time during formation of either a signal wire of said internal element or a metal wire used for power supply wiring.
 14. The semiconductor device according to claim 13, wherein said inductance element is a parallel-connection type inductance element with multilayered metal wires being connected in parallel.
 15. A memory card using the semiconductor device according to claim
 13. 16. The semiconductor device according to claim 14, wherein said semiconductor device is any one of a flash memory and a flash memory-embedded microcomputer.
 17. The semiconductor device according to claim 14, wherein said multilayered metal wires making up said inductance element are such that central points of respective areas of respective metal wires forming an inductance element upon overlapping of projection images thereof are within areas of mutually different metal wires.
 18. A multi-chip type semiconductor device comprising a plurality of semiconductor devices each including a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit connected to more than one voltage booster circuit within said plurality of stages of voltage booster circuits for controlling an output voltage near a final stage, and an internal element to which the final output voltage is supplied from said plurality of stages of voltage booster circuits, and also including within said plurality of stages of voltage booster circuits a converter circuit at least having an inductance element, a switching element, a diode and a driver circuit for driving said switching element while letting said inductance element of said converter circuit include at least a metal wire as formed by the same process as either a signal wire of said internal element or a metal wire used for power supply wiring, wherein said plurality of semiconductor devices are disposed to overlap respectively, and wherein the inductance elements within neighboring ones of said semiconductor devices are laid out in such a manner as to prevent inductance elements within the semiconductor devices from mutually overlapping in directions lying immediately above and below said inductance elements.
 19. The multi-chip type semiconductor device according to claim 18, wherein said plurality of semiconductor devices are formed on a semiconductor chip, and wherein said inductance element of said semiconductor device is formed at one half side part of the semiconductor chip whereas the inductance element of another semiconductor device lying next to said semiconductor device is at a remaining half side part of the chip.
 20. The multi-chip type semiconductor device according to claim 18, wherein said inductance element is a parallel connection type inductance element with a parallel connection of multilayered metal wiring layers.
 21. The multi-chip type semiconductor device according to claim 18, wherein said semiconductor device is a flash memory or a flash memory-embedded microcomputer.
 22. The multi-chip type semiconductor device according to claim 18, wherein said multilayered metal wires making up said inductance element are such that central points of respective areas of respective metal wires forming an inductance element upon overlapping of projection images thereof are within areas of mutually different metal wires.
 23. A semiconductor device comprising: a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage; a voltage control unit connected to more than one voltage booster circuit within said plurality of stages of voltage booster circuits, for controlling an output voltage near a final stage; and an internal element to which the final output voltage is supplied from said plurality of stages of voltage booster circuits, wherein a first stage voltage booster circuit within said plurality of stages of voltage booster circuits has a converter circuit having an inductance element, a switching element, a diode, and a driver circuit for driving said switching element, and said switching element and said diode of said converter circuit are partly disposed to underlie said inductance element.
 24. A semiconductor device comprising: a voltage step-down circuit for potentially reducing an input voltage to a final output voltage, wherein said voltage step-down circuit has a converter circuit having an inductance element, a switching element, a diode, a driver circuit for driving said switching element, and a control circuit for control of an output voltage, and said switching element and said diode of said converter circuit are partially laid out to underlie said inductance element.
 25. The semiconductor device according to claim 23, further comprising: a spirally wired first metal wire for forming said inductance element; a second metal wire connected to an outer periphery end of said first metal wire for supplying said power supply voltage; an interlayer connection wire connected to an inner periphery end of said first metal wire while being wired from said inner periphery end toward underlying diffusion layers of said switching element and said diode; and a third metal wire for connection between the diffusion layers of said switching element and said diode.
 26. The semiconductor device according to claim 24, said device has a first metal wire as spirally wired to form said inductance element, an interlayer connection wire connected to an inner periphery end of said first metal wire while being wired from said inner periphery end toward underlying diffusion layers of said switching element and said diode, a third metal wire for connection between the diffusion layers of said switching element and said diode, and a fourth metal wire connected to an outer periphery end of said first metal wire for outputting said final output voltage thus reduced in potential.
 27. The semiconductor device according to claim 23, wherein said switching element and said diode are laid out on a semiconductor substrate so that a drain-side region of said switching element and an anode-side region of said diode oppose each other, thereby having a configuration including a parallel connection of at least two or more sets of combination units of switching elements and diodes with both regions electrically coupled together.
 28. The semiconductor device according to claim 24, wherein said switching element and said diode are laid out on a semiconductor substrate so that a source-side region of said switching element and a cathode-side region of said diode oppose each other, thereby a configuration including a parallel connection of at least two or more sets of combination units of switching elements and diodes with both regions electrically coupled together.
 29. The semiconductor device according to claim 23, wherein said inductance element is such that a plurality of layers each having said first metal wire and an inter-wiring layer dielectric film are connected in parallel.
 30. The semiconductor device according to claim 23, wherein said semiconductor device is any one of a nonvolatile memory and a nonvolatile memory-embedded microcomputer.
 31. The semiconductor device according to claim 30, wherein said nonvolatile memory or said nonvolatile memory-embedded microcomputer is a flash memory or a flash memory-embedded microcomputer.
 32. A multi-chip type semiconductor device comprising a plurality of semiconductor devices each including a plurality of stages of voltage booster circuits for potentially raising a power supply voltage up to a final output voltage, a voltage control unit connected to more than one voltage booster circuit within said plurality of stages of voltage booster circuits for controlling an output voltage near a final stage, and an internal element to which the final output voltage is supplied from said plurality of stages of voltage booster circuits, wherein a first stage voltage booster circuit within said plurality of stages of voltage booster circuits has a converter circuit having an inductance element, a switching element, a diode and a driver circuit for driving said switching element, and wherein said switching element and said diode of said converter circuit are partly disposed to underlie said inductance element, wherein said plurality of semiconductor devices are disposed to overlap respectively, and wherein said inductance elements within neighboring ones of said semiconductor devices are laid out in such a manner as to prevent said inductance elements within other semiconductor devices from mutually overlapping in directions immediately above and beneath said inductance elements.
 33. The multi-chip type semiconductor device according to claim 32, wherein said plurality of semiconductor devices are formed on a semiconductor chip, and wherein said inductance element of said semiconductor device is formed at part of on half side of the semiconductor chip whereas an inductance element of another semiconductor device neighboring upon said semiconductor device is formed at part of a remaining half side of the chip.
 34. The multi-chip type semiconductor device according to claim 32, wherein each of said plurality of semiconductor devices is a nonvolatile memory or a nonvolatile memory-embedded microcomputer.
 35. The multi-chip type semiconductor device according to claim 32, wherein said nonvolatile memory or said nonvolatile memory-embedded microcomputer is a flash memory or a flash memory-embedded microcomputer. 